https://engineering.wustl.edu/news/Pages/WashU-Engineering-team-developing-novel-way-to-reduce-heat-in-CPUs.aspx842​WashU Engineering team developing novel way to reduce heat in CPUs<p>​As consumers demand more and more functions from their computers and devices, the demand also increases to improve processor performance, leading to increased power consumption and the need to manage heat. Large data centers, which house hundreds or even thousands of these processors, generate hundreds of megawatts of heat, representing 2 percent of U.S. electricity consumption and 2 percent of global carbon dioxide emissions.<br/></p><img alt="" src="/news/PublishingImages/WashU%20Engineering%20Cisco.jpg?RenditionID=1" style="BORDER:0px solid;" /><div id="__publishingReusableFragmentIdSection"><a href="/ReusableContent/36_.000">a</a></div><p>Recently, 3-D stacked chips, which lead to improved performance over traditional chips, have become more pervasive in low-power applications. To date, however, there is no commercial solution with stacked high-power memory because conventional cooling technology is unable to cool the 3-D stacked chips and maintain reliability.</p><p style="color: #000000; font-family: "times new roman"; font-size: medium;"></p><p>A team of engineers at Washington University in St. Louis is developing a technique to cool these chips with the help of a one-year, $100,000 grant from Cisco Systems Inc. The team aims to develop new thermal materials and structures, including a micro-heat exchanger, that would help to manage the heat load without compromising performance or further increasing power consumption. In the future, such a method could be applied to other systems that generate high power and high heat.</p><p style="color: #000000; font-family: "times new roman"; font-size: medium;"></p><p> <a href="/Profiles/Pages/Damena-Agonafer.aspx">Damena Agonafer, assistant professor of mechanical engineering & materials science </a>in the School of Engineering & Applied Science, is leading a group of mechanical and electrical engineers to tackle this problem from both perspectives.</p><p style="color: #000000; font-family: "times new roman"; font-size: medium;"></p><p>Working with Agonafer are <a href="/Profiles/Pages/Mark-Meacham.aspx">Mark Meacham</a> and <a href="/Profiles/Pages/Patricia-Weisensee.aspx">Patricia Weisensee</a>, both assistant professors of mechanical engineering & materials science, and <a href="/Profiles/Pages/Xuan-(Silvia)-Zhang.aspx">Xuan “Silvia” Zhang</a>, assistant professor of electrical and systems engineering. Meacham specializes in microfluidic devices; Weisensee specializes in fluid and thermal sciences and electronics cooling; and Zhang specializes in energy-efficient computing projects and hardware.</p><p style="color: #000000; font-family: "times new roman"; font-size: medium;"></p><blockquote>“Our group here at Washington University is well-suited for this, because this is multidisciplinary problem,” Agonafer said. “Not only are we focused on the thermal side, we’re also focused on the electrical optimization. Instead of tailoring a static thermal device for the worst-case hotspot, we propose to address the thermal issue from a dynamic power map perspective.”</blockquote> <p style="color: #000000; font-family: "times new roman"; font-size: medium;"></p><p>In the first year of the project, the team plans to develop a proof-of-concept, phase-routing microheat exchanger technology using nanotechnology as a base on which to develop a thermal management system for semiconductor devices, such as 3-D chips.</p><p style="color: #000000; font-family: "times new roman"; font-size: medium;"></p><p>The team has proposed a two-phase liquid cooling technology that can mitigate some of the heat coming from the stacked 3-D chips, which is expected to rise to up to 5 kilowatts per square centimeter. Today’s CPUs put out about 100 watts to 150 watts of heat per square centimeter, Agonafer said.</p><p style="color: #000000; font-family: "times new roman"; font-size: medium;"></p><p>Agonafer is improving upon a two-phase liquid cooling technology he developed while a postdoctoral researcher at Stanford University. The technology allows vapor to escape, similar to steam, while also allowing liquid to remain inside a thin, conductive porous structure.</p><p style="color: #000000; font-family: "times new roman"; font-size: medium;"></p><p>“For this 3-D chip cooling, we are flowing the liquid on the chips,” Agonafer said. “But we can’t use water in electronics, so we use dielectric liquids.”</p><p style="color: #000000; font-family: "times new roman"; font-size: medium;"></p><p>Dielectric liquids are used as electrical insulators in high voltage applications. Unlike water, which spreads when on a flat surface, the dielectric liquid expands in sort of a large hemispheric shape, similar to a solid bubble. It can have direct contact with a device and not interfere with high-frequency signals.</p><p style="color: #000000; font-family: "times new roman"; font-size: medium;"></p><p>Agonafer has a patent pending on the technology and is working with the university’s Office of Technology Management.<br/></p> <SPAN ID="__publishingReusableFragment"></SPAN><br/>Beth Miller2018-04-04T05:00:00ZA team of engineers at Washington University in St. Louis is developing a technique to cool chips with the help of a one-year, $100,000 grant from Cisco Systems Inc.

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